Conduction behaviour of low-temperature (≤600°C) polysilicon TFTs with an in situ drain doping level

Abstract

The electrical properties of low temperature (≤600°C) polysilicon thin film transistors (TFTs) are investigated as a function of temperature and drain and gate voltage. Two types of TFTs have been processed: Classical in situ Doped Drain TFTs (CDD TFTs) and Lightly in situ Doped Drain TFTs (LDD TFTs). The electrical properties of the TFT can be improved by a reduction of the in situ drain doping level. For instance the OFF state current can be significantly reduced at low drain voltage ( V ds<5 V) owing to a reduction of the local electrical field near the drain. Therefore LDD TFTs exhibit a high ON/OFF state current ratio ( I ON I OFF =4 × 10 6 ). For both TFTs the ON state current is well described by the trapping of carriers at grain boundaries located near the interface. In addition for both structures the OFF state current ( I OFF) results from various processes of trapped carrier emission at grain boundaries localized in the space charge region of the drain junction, such as pure thermal emission, Poole-Frenkel thermal emission, thermoelectronic field emission, and band to band tunneling emission.