Concatenated LFSR makes a weighted built-in logic block observation

Abstract

The length of a test sequence is reduced when using random test vector sequences with a weighted probability, provided that the probabilistic distribution in the inputs of the circuit has been optimized using a suitable method. There are algorithms that determine the probabilistic distribution for the logic 1s in the inputs of the circuit under test. In this paper, we propose a circuit structure that allows generation of random test vectors with a weighted probability, and analysis of the response, using multiple input registers implemented as BILBO registers. Accordingly, we have proceeded with the incorporation of these BIST structures in different benchmark circuits, one of them being the ALU of a communication processor.