Weighted BIST structures in the arithmetic unit of a communication processor

Abstract

BIST structures using CAR and LFSR have shown important progress in the last few years as ASIC design styles have changed from (purely small) flattened standard cells to large hierarchical designs based on multiple module types: ALUs, RAMs, ROMs etc. The weighted self/test reduces the length of test experiments and gives an improvement in the BIST operation if it is possible to implement a weighted random test vector generation with a low area overhead in the circuit under test. These structures need to be flexible enough to be adapted to the different circuit modules. The authors propose a new circuit structure to generate a random test vector with weighted probability using LFSR or CAR multiple chains with a simple concatenation. The application of these BIST structures to the design of a communication processor with self test demonstrates the capacity for improvement in the test phase in these circuits. The authors present the results of the BIST structures designed with weighted self test and the design of the arithmetic unit with a weighted self test BIST on a communication processor.