Complementary current-mirror logic

Abstract

A logic family which operates primarily on current rather than voltage levels is proposed. This family can perform with the high speed of emitter-coupled logic (ECL), and so is a suitable candidate for mainframe computer use. In addition, the inherent gate power dissipation in the absence of an input signal resembles CMOS, making large-scale integration a possibility. Simulated results using 12-GHz n-p-n and 1.2-GHz p-n-p devices show that 120-ps gate delay is possible at a 1-mW power level. The performance of a basic logic cell and ways of forming several types of logic circuits are discussed. Line-driving capability is compared with ECL, and in many situations it is found to compare very favorably in terms of energy requirements as well as line-to-line noise coupling. The potential for multilevel applications is briefly discussed. >