CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs

Abstract

Managing the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. This needs substantial overheads in both area and power. Existing logic families that minimize switching-noise generation, such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a new logic family called the current-steering CMOS (CS-CMOS) obtained by a simple modification keeping the core CMOS structure in tact to preserve its most attractive features. This family not only reduces the switching noise by a factor of ten but also delivers five times higher speed than CSL and CBL for the same power consumption. Experimental results comparing 15-stage ring-oscillators configured in the CSL and CS-CMOS families and fabricated in a 0.18 μm process show that their energy-delay-products are 6.5 fJ*ns and 1.52 fJ*ns respectively. The usefulness of this new logic family is further demonstrated by synthesizing a cell library of CS-CMOS gates and by using it to simulate benchmark circuits, a decimation filter and a frequency divider.