Comparative study of area, delay and power dissipation for LECTOR and INDEP (leakage control techniques) at 70 nm technology node

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In recent generation higher performance and high computational capability are possible by small feature size and high density of transistors in integrated circuit. In CMOS circuit as scaling down of both supply voltage (Vdd) and threshold voltage (Vt) result in increased sub-threshold leakage current hence more power dissipation. Small feature size and decrease in both Vdd and Vt has hostile delay reduction. LECTOR and INDEP are the techniques for CMOS circuit designing which mitigate leakage current without affecting the dynamic power dissipation. This paper presents the comparative study for area, delay and power dissipation of CMOS inverter for LECTOR and INDEP techniques. Simulation of INDEP Inverter and LECTOR Inverter circuit with and without body biasing has been done. The sizing effect of extra and conventional transistor is also addressed in this paper. Simulation of the circuit is done using Tanner EDA tool at 70nm with supply voltage of 1V is considered.