Modified I–V model for delay analysis of UDSM CMOS circuits

Abstract

This paper presents an I-V model for estimating the drain current of a sub-90nm MOSFET in the linear and saturation regions. The proposed model employs the dependencies of drain current on channel width and the gate voltage. It is the modification of n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -power law model introduced by Sakurai and Newton. Our model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of MOSFET drain current at lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> . The new model is compared with Modified Sakurai-Newton (MSN) current model and Extended-Sakurai-Newton (ESN) compact MOSFET model and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of CMOS inverter. The drain characteristics predicted by our model match with BSIM4 simulation with an average error of 1.33% for 90nm technology. The delay estimations of CMOS inverter using Tanner EDA tool in 90nm technology have an average error of 0.00867% and a maximum error of 0.00945%.