Compact 1T RAM Cell for System-on-Chip Application

Abstract

In this article, a 1T random access memory (RAM) cell suitable for system-on-chip application is described. The cell consists of a newly developed stack capacitor and an access transistor. The cell size is with logic process. Note that the process is fully compatible with standard logic and requires three additional mask steps for capacitor formation. It is shown that the characteristic of the transistor is not degraded by the added process for capacitor formation. No short channel effects of an n-channel metal oxide semiconductor field effect transistor (NMOS) and p-channel MOS (PMOS) are shown up to . The saturation currents of NMOS and PMOS are 600 and , respectively, at 1.8 V operation, and these values are exactly the same as those of the transistor performance fabricated with the standard logic process. Thermal processing is kept below 710°C during stack capacitor formation to prevent boron penetration in the PMOS transistor and to keep the thermal stability of cobalt silicide. The enhanced double stack capacitor structure gives a cell capacitance of 11.5 fF, and the refresh time measured at 1 Mb density exceeds 100 ms. The standby current of a 1 Mb array is about , which is comparable to that of a six-transistor static RAM cell.