Abstract
Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32[Formula: see text]nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.
Published Version
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