Abstract
This paper presents several novel CMOS, low-power, high-performance arithmetic circuits for parallel counter and multiplier designs, which are developed based on a previously proposed non-binary shift switch logic scheme. Compared with the existing well-known counterpart designs, the new circuits significantly reduce power dissipation through the use of 4-bit state signals, where no more than half of the signal bits are subject to value-change at any logic stage, while achieving high speed and small VLSI area. SPICE simulations with a 0.25 micron, 2.5-V supply process have demonstrated the superiority of the circuits.
Published Version
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