Abstract
Novel non-binary parallel counters including (7, 2), (8, 2) and (9, 2), for CMOS low-power, high performance multiplier design are presented. The circuits which utilize a non-binary arithmetic scheme, possess the following unique logic features: (1) three out of four signal bits propagating through pass transistors being 0s, (2) no more than half of the signal bits subject to value-change at any logic stage, (3) high speed, good silicon layout, and minimum interconnections.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
