Abstract
A highly regular parallel multiplier architecture along with the novel low‐power, high‐performance CMOS implementation circuits is presented. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non‐binary arithmetic logic as well as the complementary shift switch logic circuits.The proposed 64×64‐b parallel multiplier possesses the following distinct features: (1) generating 64 8×8‐b partial product matrices instead of a single large one; (2) comprising only four stages of bit reductions: first, by 8×8‐b small parallel multipliers, then, by small parallel counters in each of the remaining three stages. A family of shift switch parallel counters, including non‐binary (6, 3)∗ and complementary (k, 2) for 2 ≤ k ≤ 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non‐binary logic operates 4‐bit state signals (representing integers ranging from (0 to 3), where no more than half of the signal bits are subject to value‐change at any logic stage. This and others including minimum transistor counts, fewer inverters, and low‐leakage logic structure, significantly reduce circuit power dissipation.
Highlights
The traditional designs of parallel multipliers [1, 3,4,5,6, 17] mainly rely on the use of fast (3,2) and (4,2) parallel counter circuits for high speed
In this paper we propose a highly regular parallel multiplier design based on recently proposed unique decomposition approach for partial product matrix reductions [10]
The proposed 64 64-b parallel multiplier shows the following distinct features" (1) Distributing input bits to 64 locations using a full 4-branch tree structure, at each location generating an 88-b partial product matrix, instead of a single large one as commonly adopted by the existing designs
Summary
The traditional designs of parallel (array) multipliers [1, 3,4,5,6, 17] mainly rely on the use of fast (3,2) and (4,2) parallel counter circuits for high speed. The restoration is applied for major shift switch parallel counters such as (6, 3)* (refer to [8, 9, 1113]) It is done by a circuit, called p-type restorer (refer to dotted boxes of Fig. 7), which seems slow, but improves the overall circuit speed because it simultaneously realizes several logic functions including converting 4-bit state signal into binary output bits of carry and sums. The simulation has shown that without counting the final addition, a total delay of 4 ns for the proposed 64 64 multiplier can be achieved, and a significant reduction in power dissipation, compared with the traditional (3, 2)-(4, 2) based counterpart designs, can be achieved
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