CMOS on dual SOI thickness for optimal performance

Abstract

A novel strained SOI process with dual SOI thickness has been demonstrated for the first time. Two different SOI thicknesses (Tsi) are obtained on the same wafer for n- and p-channel devices using one additional photo masking step. Device data shows the S/D junction capacitance is reduced by 12% without any degradation in the driving current. A thicker SOI is used for p-channel devices to increase the SiGe recess depth and volume for the embedded S/D SiGe. The driving current is improved by 15% as a result of the larger compressive stress compared to a smaller SOI thickness. Dual SOI thickness is proved to be a viable strategy for independently optimizing n- and p-channel devices.