Experimental Study on Deformation Potential (<inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula>) in MOSFETs: Demonstration of Increased <inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula> at MOS Interfaces and Its Impact on Electron Mobility

Abstract

Deformation potential ( $D_{ac}$ ), which is one of the most important parameters determining the rate of electron–acoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that $D_{ac}$ increases sharply at the MOS interface. To investigate the impact of the increased $D_{ac}$ on $\mu _{e}$ , thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that $\mu _{e}$ of greater than 1100 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the $D_{ac}$ profile around the MOS interface, experimental $\mu _{e}$ of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. $\mu _{e}$ of the body-channel SOI MOSFETs is also well reproduced using the same $D_{ac}$ profile. Thus, it is concluded that $D_{ac}$ increases sharply at the Si/SiO2 interface. The accurate modeling of the increased $D_{ac}$ around the Si/SiO2 interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.