Abstract
Summary form only given. We propose a new physical model for deformation potential (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> ) at MOS interface. In the proposed model, D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> increases sharply near Si/SiO2 interfaces. D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> in SOI FETs with SOI thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> ) ranging from 4 to 60 nm is evaluated from Shubnikov-de Haas (SdH) oscillations. It is demonstrated, for the first time, that D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> is increased sharply at the MOS interface within a range of few nanometers; whereas in traditional modeling constant D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> of greater than bulk Si value has been assumed. Since SOI has two Si/SiO2 interfaces, D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> effectively increases in extremely-thin SOI (ETSOI). The increase of D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> is more evident at 300 K or under positive substrate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> ) because electrons are distributed in entire ETSOI and are affected by both the interfaces. The increased D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> results in μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> degradation in ETSOI; whereas it contributes to an increase in stress-induced μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> enhancement in thinner T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOI</sub> devices. This finding is indispensable for designing high-performance and/or low-power 3D FETs including FinFETs, ETSOI FETs, and nanowire FETs, because these FETs have more MOS interface per unit volume.
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