SDODEL MOSFET for performance enhancement

Abstract

A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated from the source and drain regions to fabricate source/drain on depletion layer (SDODEL) transistors. Under zero bias, these doped regions are fully depleted and the resulting transistor structure is termed an SDODEL MOSFET. The fully depleted regions act electrically like insulators, as in the case of silicon-on-insulator (SOI), to reduce junction capacitance. SDODEL MOSFETs with 0.16-/spl mu/m gate length are fabricated by a slightly modified CMOS process without any additional masking steps. Subthreshold slope, simulated threshold voltage V/sub t/ rolloff, and off-state leakage I/sub off/ are comparable with control devices. The junction capacitance in SDODEL MOSFETs is found to be reduced by more than 40% compared to conventional MOSFETs. Measurement of ring oscillator speeds demonstrates that SDODEL MOSFETs enable a 15% reduction in gate delay t/sub d/ for each inverter stage. SDODEL transistors provide a low-cost alternative to SOI for reduction of S/D junction capacitance.