CMOS device and interconnect technology enhancements for low power/low voltage applications

Abstract

This paper reviews current advances and future directions in the development of scaled CMOS device technologies on bulk and SOI substrates, and multilevel interconnect architectures for application to low power/low voltage ULSI. Although traditional device scaling (as per the SIA roadmap) calls for the concomitant reduction in device sizes and power supplies driven by DRAM technology generations, the achievement of ultra-low power dissipation (at V dd ≈ 1 V or less) and high speed performance (for battery operated portable systems) will accelerate scaling and drive several new engineered structures, such as vertically modulated channel doping profiles, ultra-shallow source/drain junctions and ultra-thin SOI devices that are tailored for low voltages. In addition, the development of novel low temperature processing schemes, such as Damascene, will be accelerated for integrating low K dielectrics with Al or Cu metallizations for multilevel interconnect architectures that are designed for low power. The successful incorporation of these technologies into portable electronics systems of the coming decade will require meeting the timing, manufacturability, cost and performance goals, in concert with the SIA roadmap.