Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects

Abstract

In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on temperature, SWCNTs’ diameter, and interconnect length is studied. Possibility of using SWCNT bundles as local interconnects at 7.5-nm technology node is discussed, and it is shown that SWCNT bundles with 1 nm diameter cannot be used at the first interconnect metal level. Using Cu and SWCNT bundles, multilevel interconnect architecture of a 7.5-nm ASIC macrocell is designed which reduces the number of metal levels by 27% and power dissipation by 25% compared with the multilevel interconnect architecture designed with only Cu. The effect of aspect ratio (AR) on the n-tier design is studied. It is shown that decreasing AR of SWCNT bundle interconnects, decreases total power dissipation of the ASIC macrocell by 41%. The impact of temperature variation on the design of multilevel interconnect architecture is also investigated.