High performance 70 nm CMOS device and key technologies

Abstract

The fabrication of the high performance 70 nm CMOS device has been successfully explored. Some innovation technologies such as 3 nm nitrided gate oxide, dual poly-Si gate electrode, lateral local super-steep retrograde channel doping using heavy ion implantation, Ge PAI plus LEI forming 40 nm ultra-shallow S/D extension, thin and low resistance Ti-salicide and Co/Ti-salicide etc. are investigated. By these innovations in technologies, high performance 70 nm CMOS devices with excellent SCE and good driving ability have been fabricated successfully. The 57 stage unloaded 100 nm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V respectively are achieved.