Power amplifiers in CMOS technology : a contributio to power amplifier theory and techniques

Abstract

In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers(PAs) in the mainstream CMOS technology is essential. In general, CMOS PAs require high supply-voltage to decrease the matching network losses and for high output power whereas the mainstream CMOS technology is optimized for low-voltage operation. This calls for innovative solutions. Three new approaches are presented: • Exploration of tuning methods of switching PAs for finding the optimum operation of RF PAs under given reliability, output power and efficiency conditions: Analytical design equations for the single ended Class-E PA are presented. The obtained results link all known Class-E PA design equations as well as presenting new design equations. Some of the new Class-E PAs require higher load resistance for the same output power and reliability conditions which is advantages for low-breakdown voltage technologies such as CMOS. Moreover, important advantages of sub-optimum Class-E PAs (e.g. lower peak switch voltage, larger switch (transistor) size) for CMOS are presented. • Exploration of high voltage circuit techniques to enable the RF CMOS PAs withstand high voltages: Extended-drain RF power devices achieved more than 70% PAE for 1, 2 and 3.4W output power at 2GHz in standard 65nm CMOS are presented. The power devices operate in sub-optimum Class-E mode, taking the advantage of higher output power with a slight PAE penalty in comparison to the conventional Class-E under the same input drive, load impedance and reliability conditions. A scalable layout approach in the design of power devices is introduced. The output power of the power devices scales with the device sizes without any degradation in the PAE, demonstrating that power-efficiency can be preserved for high power devices in CMOS technology. • Exploration of degradation detection and elimination methods to increase the reliable life-time of RF CMOS PAs: An approach is introduced to extend the lifetime of high voltage analog circuits in CMOS technologies based on redundancy, like that known for DRAMS. A large power transistor is segmented into N smaller ones in parallel. If a sub-transistor is broken, it is removed automatically from the compound transistor.