Chapter 7 - Low-Power Testing

Abstract

Numerous studies from academia and industry have shown the need to reduce power consumption during testing of digital and memory designs. This chapter discusses issues arising from excessive power consumption during test application and provides structural and algorithmic solutions that can alleviate the low-power test problems. Both structural and algorithmic solutions are described along with their impacts on parameters such as fault coverage, test time, area overhead, circuit performance penalty, and design flow modification. These solutions cover a broad spectrum of testing environments, including scan testing, scan-based built-in self-test (BIST), test-per-clock BIST, test compression, and memory testing. Although the solutions presented can be used to address most of the problems caused by excessive test power, not all problems have been solved. One concern is when multiple issues arise at the same time when developing low-power test solutions. For instance, almost all digital circuits today have scan chains and quite a few require test compression for test data volume reduction along with at-speed testing for screening timing defects. Thus far, solutions proposed to address the problem of low-power scan testing when both test compression and at-speed scan testing are used. Further, concerns arise from how testing is to be done when new low-power design techniques, such as dynamic power management and multiple-voltage design techniques, are employed. The idea of dynamic power management is to shut down parts of a design when they are idle.