Chapter 6 - Synthesis of On-Chip Communication Architectures

Abstract

The design of on-chip communication architectures is becoming more challenging as the number of components integrated into a single embedded multiprocessor system-on-chip (MPSoC) increases due to greater market demands for convergence devices. The increasing number of components in systems translates into more intercomponent communication that must be handled by the on-chip communication infrastructure. This chapter presents the research on techniques for efficient bus-based communication architecture synthesis. Some of these techniques focus on either bus topology design, or on the synthesis of bus protocol parameters, such as arbitration schemes, bus widths, and clock frequencies for a fixed bus topology. However, the communication architecture design space is a combination of the topology and protocol parameter spaces, and there have been approaches that also comprehensively synthesize both topology and protocol parameter values, for different design constraints. The chapter also discusses physical implementation aware synthesis and memory–communication architecture cosynthesis.