Abstract

In the history of semiconductor device fabrication, annealing is one of the critical process steps used to achieve the targeted device performance. Thermal budget requirements in most semiconductor manufacturing process steps have always followed a downward trend through either a reduction of the time spent at high temperature or a lowering of the peak temperature. This was driven at first by the traditional shrinking of structure dimensions which naturally required reducing species diffusion. From the last decade, performance improvements started to be driven essentially by the introduction of new materials (e.g., SiGe alloy, high-k/metal gate stack) and device architecture changes (e.g., 2D planar to 3D FinFET). The current development trend is leading toward 3D integrated circuits to answer the growing demand for increased functionality and performance. Such new drivers impact the whole supply chain, and low thermal budget solutions are now key to manage local strain and stress; limit species diffusion and interdiffusion; and control layer deposition, etch, and quality.

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