Chapter 15 - Design of Memory Subsystems

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This chapter illustrates memory subsystem design including addressing circuitry, memory peripherals, and special addressing circuitry for address acceleration. A memory subsystem includes physical memories, address generators, circuit around memories, and memory buses. Part of the memory subsystem (address generator) is allocated in the processor core, and the rest is allocated beside the core in the SoC. A memory subsystem is one of the three basic components of a SoC; the other two are the DSP subsystem (including cores and accelerators) and MCU cores. A DMA (direct memory access) controller and a MMU (memory management unit) as hardware peripheral modules functionally are components of the DSP subsystem. A memory module is a hardware storage component where data can be stored and retrieved to and from a physical position inside the module. Each position is specified by a unique address, and the data access (storing and retrieving) is to point to the corresponding address with associated access control (read or write). When the access control is a read, the data at the pointed position in the memory module will be available on the module output. When the access is a write, data on the data bus to the memory module will be written into the pointed position in the memory module 0. Memories can be divided into read-write memories (RAM) and read-only memories (ROM).