Chapter 3 - Direct Memory Access

Abstract

This chapter explores some intricacies that direct memory access (DMA) controller introduces such as contention for shared resources and new challenges in maintaining coherency between data buffers. It uses the Blackfin Processor's DMA controller as a model to illustrate the basic concepts of direct memory access and the way it can boost system performance. It also offers some helpful ways to manage the DMA controller and reviews examples of “two-dimensional” transfers that can save valuable data passes by markedly reducing the time an application spends traversing a data buffer. There are two main classes of DMA transfer configuration: register mode and descriptor mode. Regardless of the class of DMA, the same type of information makes its way into the DMA controller. When the DMA runs in register mode, the DMA controller simply uses the values contained in the DMA channel's registers. In the case of descriptor mode, the DMA controller looks in memory for its configuration values. When the data source and/or destination is external to the processor, a separate “Handshake DMA” mode can help throttle the memory-to-memory DMA (MemDMA) transfer and improve performance by removing the processor from having to be involved in every transfer.