Chapter 12 - Field Programmable Gate Array Testing

Abstract

This chapter provides an overview of the typical architecture and configuration features of field programmable gate arrays (FPGAs) as well as the testing challenges posed by these complex devices. With the incorporation of embedded cores including RAMs, DSPs, and processors, FPGAs more closely resemble SOC implementations. At the same time, more SOCs are incorporating embedded FPGA cores. The programmability of FPGAs facilitates the implementation of a wide range of applications and, as a result, presents a number of testing solutions as well as a number of testing challenges. The programmable logic blocks and routing resources of an FPGA core can be reprogrammed to test the other embedded cores within SOCs such as RAM and DSP cores. With algorithmic generation, execution, and diagnosis of BIST configurations from an embedded processor core, a single program can be stored and used for manufacturing testing or incorporated into the system for on-demand built-in self-test and diagnosis of the FPGA core for fault-tolerant applications. Therefore, FPGA testing techniques are becoming increasingly important for a broader range of system applications. FPGA testing challenges continue to increase with the introduction of new cores and architectures. On the other hand, these testing challenges in conjunction with the programmability of FPGAs provide an excellent platform for research and development of new SOC test architectures, strategies, and methodologies, such as silicon debug and diagnosis.