Chapter 11 - Design of Register File and Register Bus

Abstract

This chapter discusses the design of register files, including function design and physical designs of the register file and register bus. The datapath in a DSP processor usually consists of ALU, MAC, RF (register file), and instruction-level acceleration units. The datapath is the execution unit in a DSP processor consuming input data and producing results. The datapath in a DSP processor consists of MAC (arithmetic module for multiplication and accumulation), ALU (arithmetic, logic, and data manipulation unit), RF (register file), bus subsystem, and some specific functional units. The data processing in the datapath is controlled by control signals decoded by the instruction decoder in the control path. To prepare for datapath computing, operands should be available in the RF. Load and store should also be executed between RF and data memories. The design of the datapath microarchitecture is the procedure of mapping data processing and load/store instructions to the datapath hardware, with minimized hardware cost using hardware multiplexing techniques. The inputs of the datapath function design are part of the assembly manual, including ALU instructions, MAC instructions, and Load/store instructions. The physical requirements on hardware, such as power or area requirements, are also datapath design inputs. The outputs of a datapath design consist of the schematic description of datapath modules and RTL coding guidelines.