Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool

Abstract

Register files (RFs) consume significant power in low-power processors, and their specifications vary substantially for different applications. Challenges exist in identifying the appropriate RF design and optimizing RFs for different specifications. This paper not only explores methodologies of designing low power and high performance RFs and it also extends a virtual prototyping (ViPro) tool to support fast and efficient estimation of different design knobs on the overall multi-port RF macros. To enable aggressive exploration for RFs design, three bitline (BL) sensing schemes are included into ViPro along with parasitic parameters extracted from layout. Accuracy of ViPro results are within 15 % compared to full RF schematic SPICE simulation, while the simulation speed of ViPro is 5-10 times faster. An example reveals how ViPro can optimize RF design based on various specifications in a 45nm CMOS technology. Improvements of data throughput for 1R/1W port RFs are 31% and 72% at 0.5KB and 512KB, respectively, with proper BL sensing techniques. Results also show that the optimal BL sensing scheme changes with memory capacity. At 0.5KB, the lowest energy per operation decreases by 7.5% with a single-ended BL, while energy reduction is 45% with a hierarchical BL for 512KB.