Design of register file using reversible logic

Abstract

Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic design. It consists of decoder, multiplexer, memory unit, read and write units. This has been verified using VHDL. In addition to that, we have implemented the register file in the design of Content Addressable Memory (CAM) as an application.