Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Abstract

We fabricated firstly body-tied triple-gate NMOSFETs that have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 116 nm. Fabrication process steps of the devices are compatible with that of conventional bulk planar channel MOSFET technology and explained in detail in this paper. This MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I SUB/ I D than planar channel DRAM cell transistors. By optimizing process further, it is expected that cost effective body-tied triple-gate MOSFETs can be applied to real Integrated Circuits (ICs).