Abstract
Programmable multipurpose photonic integrated circuits require software routines to make use of their flexible operation as desired. In this work, we propose and demonstrate the use of a modified tree-search algorithm to automatically determine the optimum optical path in a field-programmable photonic gate array (FPPGA), based on end-user specifications, circuit architecture and imperfections in the realized FPPGA arising, for example, from fabrication variations. In such a scenario, the proposed algorithm only requires the hardware topology and the location of the connections of the FPPGA defining the optical path to be programmed. The routine is able to optimize the path over multiple and competing objectives like the overall length, accumulated loss and power consumption. In addition, should any region of the circuit suffer from any potential damage that may affect the device performance, this algorithm is also able to provide basic self-healing and fault-tolerance capabilities by supplying alternative paths through the photonic arrangement.
Highlights
Photonic integration combines multiple optical components on a chip to enable optical signal processing while maintaining a low-form factor. It has mostly been utilized in the form of Application Specific Photonic Integrated Circuits (ASPICs), where each circuit is designed and optimized to perform a particular functionality
We will demonstrate the performance of the auto-routing algorithm using two hexagonal waveguide meshes of different sizes: a 7-cell and an 18-cell configuration, containing 30 and 81 Tunable Basic Unit (TBU), respectively
Afterwards, we extend the application of our algorithm to the synthesis of optical interferometers
Summary
Photonic integration combines multiple optical components on a chip to enable optical signal processing while maintaining a low-form factor. A solution leading to mass production and subsequent cost reduction for PIC manufacturing, multi-project wafers are fabrication runs where different designs from different users are combined on the same wafer providing cost sharing [2,3,4]. Their time-to-market becomes limited by the design processes and by large development periods to minimum of 12-24 months per design-fab-packaging-test iteration, depending on the chip complexity [5]
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