Chapter 22 - Instance-Specific Design

Abstract

This chapter covers instance-specific design, an optimization technique involving effective exploitation of information specific to an instance of a generic design description. It introduces different types of instance-specific designs with examples and describes partial evaluation, a systematic method for producing instance-specific designs that can be automated. It covers the application of partial evaluation to hardware design in general and to field-programmable gate arrays (FPGAs) in particular. FPGAs are an effective way to implement designs in computationally intensive datapath-oriented applications such as cryptography, digital signal processing (DSP), and network processing. The main alternative implementation technologies in these application areas are general-purpose processors, digital signal processors, and application-specific integrated circuits (ASICs). Instance-specific design offers the opportunity to exploit the reconfigurable nature of FPGAs to improve performance by tailoring circuits to particular problem instances. It can be broadly categorized into three techniques that include constant folding, which can be applied when some inputs are static; function adaptation, which alters the function of circuitry to produce a certain quality of result; and architecture adaptation, in which the circuit architecture is adapted without affecting its functional behavior. The level of automation that can be applied varies among these approaches. Constant folding can often be carried out automatically using partial evaluation techniques. Function adaptation can be performed by varying bit widths and arithmetic methods in parameterized IP cores. Tools such as Quartz (for low-level design) or tool for stream architectures can produce highly parameterized circuit cores where design parameters can be traded off against each other to achieve the desired requirements in area, speed, and power consumption. Architecture adaptation, such as adding processing units to instruction processors, is typically much less automated. The designer must create separate implementations of the different architectures, optimizing each of them somewhat independently.