Chapter 9 - 3-D Circuit Architectures

Abstract

This chapter focuses on the performance enhancements that originate from the three-dimensional (3-D) implementation of wire-dominated circuits. It summarizes the existing performance limitations of these circuits and discusses the 3-D architectural choices and corresponding tradeoffs for microprocessors, memories, and microprocessor-memory systems. It presents 3-D topologies for on-chip networks and analyzes the extension to the third dimension of an important design solution, namely field programmable gate arrays (FPGAs). Vertical integration can improve both the latency and power consumption of wire-limited and communication-centric circuits. These circuits include the microprocessor-memory system, on-chip networks, and FPGAs. Implementing several components of a microprocessor across multiple physical planes decreases the power consumption and improves the speed by utilizing fewer redundant pipeline stages. Partitioning a cache memory into a 3-D structure can reduce the time required to access the memory. Stacking additional memory planes on a microprocessor can improve the overall performance of a microprocessor-memory system without exceeding the thermal budget of the system. 3-D NoCs are a natural evolution of 2-D NoCs and exhibit superior performance. The minimum latency and power consumption can be achieved in 3-D NoC by reducing both the number of hops per packet and the length of the communication channels. A critical issue in 3-D FPGAs is the greater complexities of the 3-D switch box that can negate the benefits from the shorter interconnect length and enhanced connectivity among the logic blocks.