Asynchronous Analogue-to-Digital Conversion Techniques

Abstract

The sensor values readout is a critical issue in Factory Automation systems and control applications in general. Analogue-to-Digital Converters (ADCs) are the circuits that accept as input the analogue indication of the sensors and provide as output the corresponding digital code representation of the analogue value that can be exploited by the digital part of the controller. The most important parameters that affect the selection of an appropriate ADC are the conversion resolution, the sampling rate, the power consumption and the die area required. Several architectures have been proposed for ADCs that target different application requirements. For example, cable TV and PAL/NTSC decoders require 8-12bits resolution with 10-20MS/s sampling rate while high speed logic analyzers require 5-7bits resolution with multi-GS/s sampling rate. The industrial systems that require ADC conversion are production lines, command-control facilities, product quality measurement, communication networks, security systems etc. Industrial systems may use ADCs for the control of simple sensors like temperature, humidity, pressure, etc as well as for the interface of input devices with increased complexity like high speed and precision imagers. The most popular ADC architectures are the Flash, Pipeline, Successive Approximation, Sigma-Delta and Folding-Interpolation ones. The Flash ADCs achieve the highest speed but occupy large silicon area and consume high power. For this reason, their resolution is practically limited to less than 8-bits. Furthermore, special analogue front-end components or technology processes need to be employed to design Flash ADCs that achieve multi-GS/s sampling rates. The Pipeline or Subrange ADCs consist of two or more ADCs with smaller resolution that operate on successive inputs in a pipelined manner and generate different groups of output bits. The throughput of pipeline ADCs is comparable to that of the Flash ADCs, the die area and power consumption are lower but the latency of a single sample is much longer. Counting and Successive Approximation ADCs consist of a digital counter that feeds a Digital-to-Analogue Converter (DAC) with increasing values until the analogue output of the DAC gets higher than the input. These ADCs require a very small number of components but need a variable large number of clock periods to reach a decision. FoldingInterpolating ADCs use a small number of comparators that compare the input successively with different sets of reference values. Finally, Sigma Delta ADCs are based on input oversampling. Parallel ADCs consist of multiple slower ADCs that are interleaved in time. 20