Improvement of pipeline ADC resolution in sequential stages of conversion

Abstract

Due to high discrepancy between possible combinations of rate and resolution of today’s analog to digital converters (ADCs) and capabilities of the digital systems in favour of the latter, improvement of ADCs performance still is and will likely long be an actual issue. A perspective class of converters that allows further improvements of conversion quality, are adaptive pipeline ADCs (APADCs). APADCs on top of having all of the virtues of pipeline ADCs, such as an excellent compromise of relatively high speed due to pipelining of conversion iterations and high accuracy, as well as relatively low complexity, sizes and power consumption, thanks to computing of codes of input samples using digital signal processing (DSP) algorithms, allow full optimization of their functioning and achievement of better performance than of conventional pipeline ADCs. Optimization of APADC requires identification of factors critically influencing performance of APADC. This work focuses on one of them - the difference between resolution of estimates computed by a given stage of APADC and resolution of feedback DACs in following stages producing their analog equivalents, which creates a need for estimates resolution reduction in the course of conversion. The influence of the latter on work and performance of APADC is analyzed in the paper and a method to compensate this influence and improve resolution of APADC in sequential stages of conversion, is developed. Results of simulation experiments that prove effectiveness of the proposed solution and allow to estimate the benefits resulting from it, are presented.