Assertion based functional verification analysis of AMBA-AHB using System Verilog

Abstract

A widely used advanced microprocessor bus architecture (AMBA) aims at easing the component design by using the combination of interchangeable components in the system-on-chip (SoC) designs (ARM Ltd., 1999). This paper presents the implementation and functional verification of widely used advanced high-performance bus (AHB) protocol of AMBA using assertion based functional verification approach. This paper contributes as follows: 1) implementation of AMBA-AHB protocol using System Verilog language in Synopsys VCS® tool; 2) assertions implementation for different components of the design; 3) functional verification of the overall design using assertions and analysis of the obtained coverage report from Synopsys VCS®. All the assertions and coverage analysis results are combined together to get the overall functional coverage of the AMBA-AHB design. The final functional coverage of the design comes out to be 97.42%. The main aim of this work is to implement AMBA-AHB protocol using System Verilog and analyse the coverage reports of different types of coverages reported by Synopsys VCS®. The result of the analysis is shown in different types of coverages to verify the completeness of the design by observing the shortcomings in the testbench and improving them for enhancing the overall functional coverage using System Verilog in Synopsys VCS®.