GF(2<SUP align="right">m</SUP>) versatile multiplier/adder architecture for cryptographic applications

Abstract

This paper describes a versatile module architecture for performing multiplication and addition in binary finite fields GF(2m), with applications to cryptography, using a polynomial basis representation. The proposed architecture provides an execution of the most significant bit (MSB)-first bit-serial multiplication for different operand lengths. This arithmetic module has cryptographic relevance, indeed the latter offers architecture with the features of high order of flexibility which allows an easy configuration for different field sizes, and low hardware complexity which results in small area. The evaluation of efficiency of the proposed architecture is based on criteria of time (latency, critical path) and space (gate-latch number).