Accessing AHB bus using WISHBONE master in SoC design

Abstract

An IP (Intellectual Property) based SoC (System-on-Chips) is getting popular among designers as it allows for a faster development cycle for SoC production. However, each IP may use different bus interface causing compatibility issues during design integration. A WISHBONE bus and an AHB (Advanced High Performance Bus) are among commonly used bus interfaces for many IP cores. This paper describes the conversion operation from WISHBONE Bus protocol into an AHB bus protocol. This is to allow an Open RISC Micro Controller Unit (ORMCU), a master device which uses WISHBONE bus protocols, to communicate and control all other devices (slaves) that use AHB bus protocols. The design is a WISHBONE-to-AHB Bridge, which consist of a WISHBONE slave and an AHB master inside one module. The simulation results confirm that the bridge is able to handle communication from a WISHBONE master in an AHB system.