Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Abstract

Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a low-power bus encoding architecture which is able to deal with the complex advanced high- performance bus (AHB) protocol within AMBA, which involves multiple burst transfers. The architecture is targeted for a low-power SoC platform to be used in a miniaturised low power application area. The paper describes the SoC platform and the bus encoding architecture, and provides results with a design synthesised at 0.35 µm CMOS technology indicating up to 22% power saving.