Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules

Abstract

Abstract System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).