Abstract
In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.
Highlights
Elliptic curve cryptography (ECC), a public key cryptography (PKC), has become a buzzword in the fields of network security, digital signatures, and radio frequency identification (RFID) [1]–[3]
This paper presents an efficient interleaved modular multiplication algorithm along with its hardware design and implementations over GF(p) for lightweight, reconfigurable ECC processors [16], where primes p are National Institute of Standard and Technology (NIST)-recommended [17], [18]
In order to reduce the time complexity of elliptic curve scalar multiplication (ECSM) over GF(p) as well as the hardware resource requirements for ECC, we propose an area-time efficient modular multiplier, introducing a modified radix-2 interleaved modular multiplication algorithm
Summary
Elliptic curve cryptography (ECC), a public key cryptography (PKC), has become a buzzword in the fields of network security, digital signatures, and radio frequency identification (RFID) [1]–[3]. Over the past few years, field-programmable gate array (FPGA)-based ECC schemes have been drawing extensive attention of security researchers by offering a number of advantages over other software-based cryptographic platforms. Their re-programmability, reconfigurability, optimization capability, lower latency, and higher throughput make them more convenient for the IoT security. Islam et al.: Area-Time Efficient Hardware Implementation of Modular Multiplication prime number. This paper presents an efficient interleaved modular multiplication algorithm along with its hardware design and implementations over GF(p) for lightweight, reconfigurable ECC processors [16], where primes p are National Institute of Standard and Technology (NIST)-recommended [17], [18].
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
