Abstract
The study presents an analytical model for the switching voltage and gain factor of a CMOS inverter with 2D nanochannel transistors. The derived expressions enable the modeling of these two fundamental parameters of the device, which serves as the basement for logic elements in contemporary nanoelectronics. The feasibility of creating efficient inverters with a high gain factor based on transistors with channels made of 2D monolayers of transition metal dichalcogenides and arrays of carbon nanotubes has been confirmed. It was demonstrated that the gain factor is restricted by the drain induced barrier lowering (DIBL) effect, which is undesirable for FETs (when DIBL trends to zero the gain factor becomes infinitely large).
Published Version
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