Analytical I–V and C–V models for symmetric double-gate AOSTFTs

Abstract

In this article we present a full physical analytical model (FAM) for symmetric double-gate amorphous oxide semiconductor TFTs (DG AOSTFTs). The current–voltage (I–V) model is physically described for the above-threshold operation regime. In this case, the general expression for the field effect mobility is evaluated for the potential at the centre of the semiconductor layer at V G= 1 + V T, obtaining the value of the mobility parameter called µ 1DG for DG-AOSTFT. This parameter can now be used to represent the field effect mobility expression like in the model known as the unified model and extraction method, which is widely used for modelling amorphous devices. The proposed FAM model contains the analytical capacitances–voltage (C–V) model and considers the specific characteristics of DG structures, including the potential different from zero, at the centre of the semiconductor layer. The model was described in Verilog-A for introducing in Silvaco’s SmartSpice simulation program and was validated with simulated data and experimental characteristics of reported DG amorphous indium-galium-zinc oxide devices.