Analysis of Static Noise Margin of 10T SRAM Using Sleepy Stack Transistor Approach

Abstract

The latest electronic gadgets demand many functionalities which requires enhanced performance of the processor. To ensure this, cache based on Static Random Access Memory (SRAM) is a vital part in electronic devices. Above 90 nm technology, we can build an SRAM in CMOS LSI technology without electrical stability, by connecting six transistors. However, leakage and variability of transistors in SRAM cell have become dominating factor below 90nm technology. So we must design SRAM bit cell with utmost care. Recently SRAM cells have been designed to deal with these problems. However, it is an important task to achieve a balanced performance between all SRAM cell parameters of sub-nanometer technology. A new design of SRAM is presented in this paper to elevate the performance. The proposed SRAM is designed and implemented in CMOS 90nm technology and produces comparatively better performance in terms of Static Noise Margin (SNM), stability and power dissipation when compared with conventional 6T SRAM. The cell reduces the energy consumption by using the technique of stacking. The stability of proposed SRAM is also high compared to recent designs.