An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm

Abstract

This paper presents a clock and data recovery (CDR) topology that can adjust the power consumption with its input bit-rate. Current-mode structures are utilized to control the power consumption. The system is comprised of a phase detector, a charge pump, a second-order filter, a voltage-to-current converter, a bias controller, and a current controlled oscillator. In order to attain an ultra-low power profile, subthreshold source-coupled logic (STSCL) is used to implement the system blocks. A modified version of low-voltage current-mirror is proposed and utilized to improve the thermal stability of the CDR structure. The proposed current mirror improves the oscillator frequency variation more than 20 times. The CDR is simulated in 90 nm standard CMOS process with VDD = 1 V. It can recover clock frequencies between 1 MHz and 25 MHz. The corresponding power consumption is between 195 nW and 450 nW, and the measured deterministic-jitter is less than 100 ns.