An Efficient Wide Range 2.45 ns, 4.38 nW Subthreshold Voltage Level Shifter Using 45 nm CMOS Technology

Abstract

The design of system-on-chip (SoC) architectures has in recent years been characterized by combination of different circuits operating at different supply voltage based on their timing needs. To interface multiple voltage domains and to maintain total performance in multiple-VDD systems, reliable level shifter circuits are a must. Through the use of different supply voltages, the voltage level shifter establishes a proper connection among different blocks. The level shifter converts low voltage to higher voltages that are acceptable to the next stage. In this sense, the level shifter serves an important role in multiple supply circuits. The level shifter should be low-power, fast and should occupy small silicon area so that effect on overall system performance would be less. Here, a high speed voltage level shifter with improved range of conversion is proposed. With relatively fewer elements, the level shifter is more compact, exhibits a much lower propagation delay, and allows for very low sub threshold input voltages. Proposed voltage level shifter is provided using the cadence virtuoso design in 45 nm technology. This level shifter shifts voltage input in the range of 75 mV to 1.1 V. It exhibits a delay of 2.45 ns and total power of 4.38 nW.