Design and Implementation of Multiple-Output CMOS Voltage Level Shifter

Abstract

Different parts such as digital, analog, passive components are manufactured on a single chip in system on chip (SoC) design and require different voltages to achieve optimum performance. The voltage level shifter (LS) is a device that changes over level of voltage to other level of voltage. Different circuit squares working at various supply voltages are interfaced with voltage LS. The SoC voltage LS is used at the edge of various islands of voltage. Single-output and multiple-output CMOS LS are implemented. The proposed voltage LS converts low voltage input to high voltage output with higher speed and lower power consumption. The design of the architecture is implemented using CMOS technique. Multi-threshold voltage CMOS technology is used to decrease power and delay when designing the voltage LS. To minimize delay, device with low-threshold voltage is used. Using high-threshold voltage devices, power dissipation can be reduced. In 45 nm technology, the design was implemented. Comparison is made of the power dissipation and propagation delay.