AN ARCHITECTURE OF DATAFLOW LSP FOR PROGRAMMABLE CONTROLLERS

Abstract

An architecture of the logic solving processor based on the dataflow structure and its mathematical modeling are proposed in this paper. The proposed dataflow logic solving processor(DFLSP) is designed based on the dataflow architecture in order to have the fine grain concurrency and the data synchronization capability. The logic program language for the programmable controller(PC) is formalized using a dataflow graph, and with this formalized dataflow graph, the operation of DFLSP is described. The proposed DFLSP can solve 1000 instructions in 195 μsee with one processing unit and in 75 μsec with four processing units at 20 MHz clock speed.