An analysis about increasable latch overhead time for processor pipeline depth increase

Abstract

For a processor of pipeline configuration, we use a performance model based on mathematical expressions to study the pipeline increasable latch overhead time when the performance is increased by increasing the number of pipeline stages. When a performance increase is attempted by further increasing the number of stages for a processor in which the number of stages is more than 90% of the optimum for performance, the performance is found not to be increased unless the increasable latch overhead time is less than the overhead time. Also, the ratio of the increasable latch overhead time to the clock cycle time reduced by the increased number of stages is shown to be smaller in a linear manner for the increased number of stages. The increasable latch overhead time is a factor influencing the limit of performance improvement by an increased pipeline. In future deep pipeline processors, a circuit design technique that guarantees this increasable time and a timing design tool that verifies this improvement are needed. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(5): 29–36, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20127