A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories

Abstract

As the microprocessor speed increases from500MHz to 1GHz and beyond, SOC designers areforced to innovate new schemes in their use of cachememory for high speed access. In this paper, clock towordline path delay is optimized using a novel circuitdesign technique. Using this novel circuit, clock toword line path delay is optimized by 2.5 times at worstcase corner. For a typical memory instance frequentlyused in cache memories) whose access time is of theorder of 800ps and where read and write operationoccurs in the same clock cycle, overall access time isimproved by 18% at worst case corner. For this case,write margin is improved by 2.26 times at worst casecorner for write operation. A decoding scheme is alsodiscussed in this paper which describes how to choosethe best pre-decoding and post-decoding schemesbased on minimum pre-decoded lines, minimum stacksize in post decoder and maximum granularity of xdecoders.